Complementary MOS offers an inverter with near-perfect characteristics such as high, symmetrical noise margins, high input and low output impedance, high gain in the transition region, high packing density, and low power dissipation. Speed is the only restricting factor, especially when large capacitors must be driven. In contrast, the ECL gate has a high current drive per unit area, high switching speed, and low I/O noise. For similar fanouts and a comparable technology, the propagation delay is about two to five times smaller than for the CMOS gate. However, this is achieved at a price. The high power consumption makes very large scale integration difficult. A 100k-gate ECL circuit, for instance, consumes 60 W (for a signal swing of 0.4 V and a power supply of 4 V). The typical ECL gate also has inferior dc characteristics compared to the CMOS gate?lower input impedance and smaller noise margins.
In recent years, improved technology has made it possible to combine complimentary MOS transistors and bipolar devices in a single process at a reasonable cost. A crosssection of a typical BiCMOS process is shown in Figure 1. A single n-epitaxial layer is used to implement both the PMOS transistors and bipolar npn transistors. Its resistivity is chosen so that it can support both devices. An n+-buried layer is deposited below the epitaxial layer to reduce the collector resistance of the bipolar device, which simultaneously increases the immunity to latchup. The p-buried layer improves the packing density, because the collector-collector spacing of the bipolar devices can be reduced. It comes at the expense of an increased collector-substrate capacitance. This technology opens a wealth of new opportunities, because it is now possible to combine the high-density integration of MOS logic with the current-driving capabilities of bipolar transistors. A BiCMOS inverter, which achieves just that, is discussed in the following section. We first discuss the gate in general and then provide a more detailed discussion of the steady-state and transient characteristics, and the power consumption. The section concludes with a discussion of the usage of BiCMOS and the future outlook. Most of the techniques used in this section are similar to those used for CMOS and ECL gates, so we will keep the analysis short and leave the detailed derivations as an exercise.
Figure 1 Cross-section of BiCMOS process
BICMOS GATE AT A GLANCE
As was the case for the ECL and CMOS gates, there are numerous versions of the BiCMOS inverter, each of them with slightly different characteristics. Discussing one is sufficient to illustrate the basic concept and properties of the gate. A template BiCMOS gate. When the input is high, the NMOS transistor M1 is on, causing Q1 to conduct, while M2 and Q2 are off. The result is a low output voltage. A low Vin, on the other hand, causes M2 and Q2 to turn on, while M1 and Q1 are in the offstate, resulting in a high output level. In steady-state operation, Q1 and Q2 are never on simultaneously, keeping the power consumption low. An attentive reader may notice the similarity between this structure and the TTL gate, described in the addendum on bipolar design. Both use a bipolar push-pull output stage. In the BiCMOS structure, the input stage and the phase-splitter are implemented in MOS, which results in a better performance and higher input impedance.
The impedances Z1 and Z2 are necessary to remove the base charge of the bipolar transistors when they are being turned off. For instance, during a high-to-low transition on the input, M1 turns off first. To turn off Q1, its base charge has to be removed. This happens through Z1. Adding these resistors not only reduces the transition times, but also has a positive effect on the power consumption. There exists a short period during the transition when both Q1 and Q2 are on simultaneously, thus creating a temporary current path between VDD and GND. The resulting current spike can be large and has a detrimental effect on both the power consumption and the supply noise. Therefore, turning off the devices as fast as possible is of utmost importance.
The following properties of the voltage-transfer characteristic can be derived by inspection. First of all, the logic swing of the circuit is smaller than the supply voltage. Consider the high level. With Vin at 0 C, the PMOS transistor M2 is on, setting the base of Q2 to VDD. Q2 acts as an emitter-follower, so that Vout rises to VDD ? VBE(on) maximally. The same is also true for VOL. For Vin high, M1 is on. Q1 is on as long as Vout > VBE(on). Once Vout reaches VBE(on), Q1 turns off. VOL thus equals VBE(on).1 This reduces the total voltage swing to VDD ? 2VBE(on), which causes not only reduced noise margins, but also increases the power dissipation. Consider for instance the circuit of Figure 0.2, where the BiCMOS gate is shown with a single fan-out for Vin = 0. The output voltage of VDD ? VBE(on) fails to turn the PMOS transistor of the subsequent gate completely off, since VBE(on) is approximately equal to the PMOS threshold. This leads to a steady-state leakage current and power consumption. Various schemes have been proposed to get around this problem, resulting in gates with logic swings equal to the supply voltage at the expense of increased complexity. Some of these schemes will be discussed later. Aside from this difference, the VTC of the BiCMOS inverter is remarkably similar to that of CMOS.
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