LDPC Codes

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Due to their near Shannon limit performance and inherently parallelizable decoding scheme, low-density parity-check (LDPC) codes. have been extensively investigated in research and practical applications. Recently, LDPC codes have been considered for many industrial standards of next generation communication systems such as DVB-S2, WLAN (802.11.n), WiMAX (802.16e), and 10GBaseT (802.3an). For high throughput applications, the decoding parallelism is usually very high. Hence, a complex interconnect network is required which consumes a significant amount of silicon area and power.
A message broadcasting technique was proposed to reduce the routing congestion in a fully parallel LDPC decoder. Because all check nodes and variable nodes are directly mapped to hardware, the implementation cost is very high. The decoders in are targeted to specific LDPC codes which have very simple interconnection between check nodes and variables nodes. The constraints in H matrix structure for routing complexity reduction unavoidably limit the performance of the LDPC codes. The LDPC code decoder proposed in based on two-phase message-passing (TPMP) decoding scheme.
Recently, layered decoding approach has been of great interest in LDPC decoder design because it converges much faster than TPMP decoding approach. The 4.6 Gb/s LDPC decoder presented in adopted layered decoding approach. However, it is only suited for array LDPC codes, which can be viewed as a sub-class of LDPC codes. It should be noted that a shuffled iterative decoding algorithm based on vertical partitioning of the parity-check matrix can also speed up the LDPC decoding in principle.
In practice, LDPC codes have attracted considerable attention due to their excellent error correction performance and the regularity in their parity check matrices which is well suited for VLSI implementation. In this paper, we present a high-throughput low-cost layered decoding architecture for generic QC-LDPC codes. ? A row permutation approach is proposed to significantly reduce the implementation complexity of shuffle network in the LDPC decoder. An approximate layered decoding approach is explored to increase clock speed and hence to increase the decoding throughput. An efficient implementation technique which is based on Min-Sum algorithm is employed to minimize the hardware complexity. The computation core is further optimized to reduce the computation delay.
Low-density parity-check (LDPC) codes were invented by R. G. Gallager (Gallager 1963; Gallager 1962) in 1962. He discovered an iterative decoding algorithm which he applied to a new class of codes. He named these codes low-density parity-check (LDPC) codes since the parity-check matrices had to be sparse to perform well. Yet, LDPC codes have been ignored for a long time due mainly to the requirement of high complexity computation, if very long codes are considered. In 1993, C. Berrou et. al. invented the turbo codes (Berrou, Glavieux, and Thitimajshima 1993) and their associated iterative decoding algorithm. The remarkable performance observed with the turbo codes raised many questions and much interest toward iterative techniques. In 1995, D. J. C. MacKay and R. M. Neal (MacKay and Neal 1995; MacKay and Neal 1996; Mackay 1999) rediscovered the LDPC codes, and set up a link between their iterative algorithm to the Pearl?s belief algorithm (Pearl 1988), from the artificial intelligence community (Bayesian networks). At the same time, M. Sipser and D. A. Spielman (Sipser and Spielman 1996) used the first decoding algorithm of R. G. Gallager (algorithm A) to decode expander codes.

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