One of the constants in computer technology is the continuing advancement in operational speed. A few years ago, a 66 MHz PC was considered ?lightning fast?. Today?s common desktop machine operates at many times that frequency. All this speed is the foundation of a trend towards visual computing, in which the PC becomes ever more graphical, animated, and three- dimensional..
In this quest for speed, most of the attention is focused on the microprocessor. But a PC?s memory is equally important in supporting the new capabilities of visual computing. And commodity Dynamic RAMs (DRAMs), the mainstay of PC memory architecture, have fallen behind the microprocessor in their ability to handle data in the volume necessary to support complex graphics. While device densities have increased by nearly six orders of magnitude, DRAM access times have only improved by 10. Over the same time, microprocessor performance has jumped by a factor of 100. In other words, while bus frequency has evolved from 33 MHz for EDO to the current standard of 100 Mhz for SDRAMs and up to 133 MHz for the latest PC-133 specification, memory speed has been out spaced by the operation frequency of the microprocessor which reached 600 MHz plus by the turn of the century. Thus, the memory subsystem risked to become a bottleneck for overall system performance or had created a significant performance gap between computing elements and their associated memory devices.
Traditionally, this gap has been filled by application specific memories like SRAM caches, VRAMs etc. In order to broaden the usage, we thus need a high density, low cost, high bandwidth DRAM.
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This technology is based on a very high-speed, chip-to-chip interface and has been incorporated into DRAM architectures called Rambus DRAM or RDRAM. It can also be used with conventional processors and controllers to achieve a performance rate that is 100 times faster than conventional DRAMs. At the heart of the Rambus Channel Memory architecture, is ordinary DRAM cells to store information. But the access to those cells, and the physical, electrical and logical construction of a Rambus memory system is entirely new and much, much faster than conventional DRAMs. The Rambus channel transfers data on each edge of a 400 MHz differential clock to achieve an 800- MB/s data rate. It uses a very small number of very high speed signals to carry all the address, data and control information, greatly reducing the pin count and hence cost while maintaining high performance levels. The data and control lines have 800-mV logic levels that operate in a strictly controlled impedance environment and meet the specific high-speed timing requirements. This memory performance satisfies the requirements of the next generation of processors in PCs, servers, workstations as well as communications and consumer applications.
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