THEORY: - IIR filter Designing
In the design of frequency. Selective filters, the desired filter characteristics are specified in the frequency domain in terms of the desired magnitude and phase response of the filter. In the filter design process, we determine the coefficients of a causal IIR filter that closely approximates the desired frequency response specifications. An Infinite impulse response (IIR) filter possesses an output response to an impulse which is of an infinite duration. The impulse response is "infinite" since there is feedback in the filter, that is if you put in an impulse ,then its output must produced for infinite duration of time.
The sigma-delta modulator based closed loop systems make high resolution, high SNR, low frequency systems. The sigma-delta analog to digital converter consists of the modulator followed by the decimation filter. In this project the design of decimation filter, which performs the role of filtering the shaped quantization noise and converting 1-bit data stream into 20 bit high-resolution output is reported.
An efficient multi-stage decimation methodology is adapted where decimation is performed in several stages due to high order of the decimation filter which is almost impossible to implement in hardware. The multi-stage structure consists of Cascaded Integrator Comb (CIC) filter followed by FIR. The specifications of decimation filter are derived from the specifications of a third-order single bit sigma-delta modulator. Use of cascaded integrated comb filter for the first stage has made the implementation easy by requiring no multiplication. Furthermore, it can be used to decimate the data by a large factor, allowing easier implementation of the following stages. Distributed arithmetic algorithm is used to design FIR filters. Software model for the decimation filter is developed using MATLAB /Simulink, and integrated with sigma-delta modulator model to analyze the responses. The hardware model for the filter is developed using Verilog HDL.
The design is implemented and tested using SPARTAN 3E FPGA. Filter has got pass band of 100Hz and stopband of 200Hz .The test environment has the feature of taking external input as well as the internally stored bit stream in LUT. The designed system exhibits good linearity and the design consumes a power of 40.4mW.
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